RF CMOS Design Engineer in MA

I have a position with a very exciting, cutting edge start up company here in MA. They are currently seeking an RF CMOS Design Engineer with good device physics and circuit analysis skills.

Required Qualifications

• MSEE or PhD in electrical engineering

• Experience with design, simulation and layout of analog and mixed-signal integrated circuits

• Solid understanding of CMOS device physics and circuit analysis

• High level of analytical sophistication

• Proven track record of successful product development

• Good written and verbal communications skill

• Solid problem-solving and trouble-shooting skills

• Highly motivated and be able to work both independently and as a team member

• Proficiency with Cadence and Mentor Graphics tools

Desired Qualifications

• 5 or more years of professional experience

• Experience with Verilog-AMS modeling

• Familiar with Cadence SKILL language

• Experience in MATLAB, C/C++ and Java languages

• Experience in scripting language like Perl and Tcl

• Experience working in a start-up environment

• US citizenship or permanent resident

For more information or if you are interested, please send your resume to Ross@hightechnh.com

Memory Circuit Designer for DDR Interface and Control Block Circuitry (AUSTIN)

Memory Designer for DDR Interface and Control Block Circuitry

Ross Cooper is searching for exceptional candidates to fill a Member of the Technical Staff position in MRAM circuit design (Austin, TX.) Please e-mail me directly, ross@hightechnh.com

Scope of Responsibility/Expectations
Work closely with other members of a small, focused, team with responsibility for designing both the pads and the control circuitry associated with a DDR interface. Design at the transistor level circuitry in the control block sitting between the DDR pads and the standard memory signals going to and from the array. This control block decodes the instructions from the bus, lines up input and output signals with the high frequency clock using DLLs or PLLs, and converts input signals to array commands and takes array output signals, such as, data, and sends them to the pads following the DDR standard protocol. Work under the supervision of a senior project leader. Design, simulate, and supervise layout of blocks of circuitry. Work with product and test engineers evaluating and debugging circuit performance after silicon processing.

Specific Required Knowledge
• Circuit theory
• PLL/DLL design techniques
• Probability and statistics
• Logic design
• Impact of layout parasitic capacitance and resistance on signal integrity, speed, and power dissipation, along with layout techniques to minimize these effects
Useful Skills
• Transistor level simulation
• Parasitic extraction
• Critical path modeling
• Physical design, i. e., layout
• Logic verification
• Mixed-mode Verilog

Education and Experience
Masters or equivalent in Electrical Engineering, Physics, Computer Science, or related fields. A track record of placing memory chips into production is required. Experience designing DDR pads that meet JEDEC electrical specifications and that have industry standard ESD tolerance is desired. Experience with DRAMs or with DRAM Controller s and PHYs is applicable. Demonstration of innovation and leading-edge expertise through publications and patents is desired.

Send resume to: Ross@hightechnh.com