Location: Westford, MA
The Westford office seeks an experienced (BS +10, MS +8 years) Networking Architect (System/ASIC) to work on the next generation of high speed networking products. Experience with networking related designs and specific experience with QOS, queuing, and scheduling is required.
Responsibilities include system architecture, ASIC definition, micro-architecture, and project leadership. This position will require a modest amount of travel to Sunnyvale to interact and collaborate with other corporate architects. Additional responsibilities include Verilog RTL coding and synthesis, working closely with Design and Verification engineers to ensure design quality and involvement with PD engineers to ensure solid implementation and timing closure.
Will be a primary member of a team responsible for executing project deliverables and processes necessary to successfully specify, develop, and release to production highly integrated ASICs.
Primary interfaces include architecture, marketing, design, verification, product & test engineering, and other hardware and software development groups. Must have previous experience in organizations with custom / semi-custom CMOS ASIC designs. Experience required in RTL coding, verification, gate level simulation, and associated tools. Experience in physical design (place and route, static timing analysis, package selection and design for test) is a plus.
Job Requirements
We are looking for a positive, energetic candidate who would welcome the challenge of working for a leading edge, growing company. The position will involve close, consultative working relationships with engineers from other teams. An outgoing personality and a collaborative spirit is required.
Required skills include:
- Design Experience
System and ASIC architecture for networking products
Knowledge of ASIC development tools, physical design tools, and
programming languages, QOS, packet queuing, and scheduling experience
Other desirable skills
SystemC, Vera, or equivalent
C/C++
Scripting with Perl and/or TCL
Large ASIC floorplanning and timing closure
Exceptional written & verbal communication skills
Location: Westford, MA
Summary
The Westford office seeks an experienced (BS +6, MS +4 years) ASIC design engineer on the next generation of high speed networking products. Experience with networking related designs is preferred.
The engineer in this position will be responsible for designing and verifying sections within our multi-million+ gate next-generation SOCs. These high performance designs will be part of the next generation of high performance network infrastructure systems.
Responsibilities
Responsibilities include Verilog RTL coding and synthesis, working closely with other design and verification engineers to ensure design quality and with PD engineers to ensure routable implementation and timing closure.
Candidate will be part of a team responsible for executing project deliverables and processes necessary to successfully specify, develop, and release to production highly integrated ASICs.
Primary interfaces include architecture, design, verification, product & test engineering, and other hardware and software development groups. Must have previous experience in organizations with custom / semi-custom CMOS ASIC designs. Experience required in RTL coding, formal verification, gate level simulation, debug and associated tasks. Experience in physical design (place and route, static timing analysis, package selection and design for test) is a plus.
Additional responsibilities
RTL development from concept to production
Participate in review of design implementation for optimal design tradeoffs and
coding styles
Ensure completed assignments meet project deadlines and departmental and
corporate goals
Participate in methodology improvement
We are looking for positive, energetic candidates who would welcome the challenge of working for a leading edge, growing company. The position will involve close, consultative working relationships with engineers from other teams. An outgoing personality and a collaborative spirit is required.
Required skills include
Bachelor's degree in Electrical Engineering or a related field
Knowledge of ASIC development tools, physical design tools, and
programming languages
Verilog, Synopsys
Ability to speak, listen and write effectively
Ability to work well with others, across geographical boundaries
Other desirable skills
SystemC, or equivalent
C/C++
Scripting with Perl and/or TCL
Large ASIC floor-planning and timing closure
Location: Westford, MA
Summary
The Westford office seeks an experienced (BS +6, MS +4 years) ASIC design verification engineer on the next generation of high speed networking products. Experience with networking related designs is preferred.
The engineer in this position will be responsible for verifying sections within our multi-million+ gate next-generation SOCs. These high performance designs will be part of the next generation of high performance network infrastructure systems.
Responsibilities
Responsibilities include writing test plans, building verification test benches, and writing / executing / debugging tests and working closely with system architects and design engineers to ensure design quality.
Candidate will be part of a team responsible for executing project deliverables and processes necessary to successfully specify, develop, and release to production highly integrated ASICs.
Primary interfaces include architecture, design, verification, product & test engineering, and other hardware and software development groups. Must have previous experience in organizations with custom / semi-custom CMOS ASIC designs. Experience required in RTL coding, verification, gate level simulation, and associated tools. Experience in physical design (place and route, static timing analysis, package selection and design for test) is a plus.
Additional responsibilities
Responsible for design verification from concept to production
Develop detailed and comprehensive test plans
Develop verification infrastructure
Timely execution of test plans
Participate in review of design verification coding and coverage metrics
Ensure completed assignments meet project deadlines and departmental and corporate goals
Participate in methodology improvements
Required skills include
Bachelor's degree in Electrical Engineering or a related field
Knowledge of ASIC verification tools, scripting and programming languages
Must be fluent in Verilog, C, and C++
SystemC knowledge is a plus
Ability to speak, listen and write effectively
Ability to work well with others, across geographical boundaries
Any interested parties, please forward your resume to me directly at ross@hightechnh.com
